`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date:    22:39:58 06/23/2014 
// Design Name: 
// Module Name:    ecc_cal 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
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module ecc_cal
(
      input [31 : 0] data, 
		output [7 : 0] ecc_code                            
);
    
	wire [7:0] byte0 = data[7:0];
	wire [7:0] byte1 = data[15:8];
	wire [7:0] byte2 = data[23:16];
	wire [7:0] byte3 = data[31:24];
	
	wire [7:0] temp0 = byte0 ^ byte1 ^ byte2 ^byte3;
	
	wire p0 = temp0[1:1] ^ temp0[3:3] ^ temp0[5:5] ^ temp0[7:7];
	wire p1 = temp0[2:2] ^ temp0[3:3] ^ temp0[6:6] ^ temp0[7:7];
	wire p2 = temp0[4:4] ^ temp0[5:5] ^ temp0[6:6] ^ temp0[7:7];
	
	wire [7:0] temp1 = byte1 ^ byte3;
	wire p3 = temp1[0:0] ^ temp1[1:1] ^ temp1[2:2] ^ temp1[3:3] ^ temp1[4:4] ^ temp1[5:5] ^ temp1[6:6] ^ temp1[7:7];
	
	wire [7:0] temp2 = byte2 ^ byte3;
	wire p4 = temp2[0:0] ^ temp2[1:1] ^ temp2[2:2] ^ temp2[3:3] ^ temp2[4:4] ^ temp2[5:5] ^ temp2[6:6] ^ temp2[7:7];
	
	wire [7:0] temp3 = byte0 ^ byte1;
	wire p4_ = temp3[0:0] ^ temp3[1:1] ^ temp3[2:2] ^ temp3[3:3] ^ temp3[4:4] ^ temp3[5:5] ^ temp3[6:6] ^ temp3[7:7];
	
	assign ecc_code = {2'b00, p4_, p4, p3, p2, p1, p0};
	
endmodule
